1. Field of the Invention
This invention relates to a semiconductor memory device and a method of manufacturing the same and, more particularly, it relates to a semiconductor memory device having a stacked capacitor cell structure and a method of manufacturing the same.
2. Description of the Related Art
As the dynamic random access memory (DRAM) proceeds the way of development for large scale integration, the area allowed for its capacitor to occupy in the device is diminished, bringing forth serious problems such as erroneous data retrievals, destruction of stored data by radiation, etc.
There have been made proposals to solve these problems by producing capacitors with improved structures. One such improvement is the stacked capacitor cell structure. FIG. 1 illustrates a typical known configuration of the stacked capacitor cell structure. In FIG. 1, reference numeral 50 denotes a semiconductor substrate, 51 a field oxide selectively formed on the substrate surface for device isolation, 52 a gate oxide formed on the substrate surface, 53 a gate electrode (word line) of a MOS transistor to be used as a transfer gate and 54 source/drain diffusion layers of said MOS transistor. The surface of the MOS transistor formed on the semiconductor substrate is covered with an inter-layer insulation film 55, through which a contact hole is bored, a lower capacitor electrode (storage node electrode) 56 being formed in such a manner that they are kept in touch with either of the source/diffusion layers 54 through the contact hole, an upper capacitor electrode (cell plate electrode) 58 being formed on said lower capacitor electrode 56 with the interposition of a capacitor gate insuation film 57, so that there is provided a MIM (metal-insulator-metal) capacitor for storing electric charges constituted by the lower capacitor electrode 56, the capacitor gate insulation film 57 and the upper capacitor electrode 58.
A stacked capacitor cell structure as described above can provide a sufficiently large area for a capacitor by enlarging the surface area of the lower capacitor electrode 56 without increasing the plane area exclusively occupied by memory cells.
However, such a conventional stacked capacitor cell structure is inevitably accompanied by a problem to be described below, if a higher level of integration is called for.
In order to provide a sufficiently large capacity for the capacitor by enlarging the surface area of the lower capacitor electrode 56, its lateral sides should carry a film at least as thick as 3,000 .ANG. for their effective use. It is extremely difficult to finely work a lower capacitor electrode having such a film thickness and consequently adjacently located lower capacitor electrodes can be mutually short-circuited when they are worked.
Thus, any known methods of manufacturing a semiconductor memory device having a stacked capacitor cell structure is accompanied by the drawback as described above of forming thick films for the lower capacitor electrode that defy fine processes to be applied to them and can result in short-circuited lower capacitor electrodes and other similar troubles.
In view of the above described problem, it is, therefore, the object of the present invention to provide a semiconductor memory device having a stacked capacitor cell structure suitable for large scale integration and capable of providing a satisfactorily large memory capacity by arranging a lower capacitor electrode with such a sufficiently large surface area that eliminates any risk of short-circuiting to arise between adjacently located lower capacitor electrodes as well as a method of manufacturing the same.